Erasmus - FPGA Implementation of Low Power CORDIC Processor for DSP Application


The COordinate Rotational DIgital Computer (CORDIC) algorithm is a well-known iterative technique to perform various basic arithmetic operations.

The algorithm is very attractive for hardware implementation because it uses only elementary shift-and-add steps to perform vector rotation in a two-dimensional (2-D) plane. Hence, the CORDIC algorithm can be applied to many DSP applications where rotation-based arithmetic functions are heavily utilized, such as singular value decomposition, fast Fourier transform and digital filters. 

In this perspective, the objective of the internship is to provide an FPGA implementation of a low power consumption CORDIC processor for square root and hyperbolic functions computation. The tasks to be accomplished are the followings: 

1-To implement the CORDIC algorithm for square root and hyperbolic functions. 

2-To synthesize the implemented design to get results in terms of resources utilization, time latency and power consumption.

3-To analyze the behavior of the implementation when the number of bits varies, and to select an effective resolution. 

4-To study new methods and implementation scenarios to reduce the power consumption. 

5-To propose a method and apply it to the CORDIC processor. 

6-To assess the implementation results by highlighting the reduction in the power consumption and its effects on the resources utilization and time latency. 

Qualifications: VHDL, Digital Signal Processing, MATLAB. 

Duration: 6 months



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