UnderG - Integrated Electronic System (M. Valle, L. Noli, A. Ibrahim)

(Master Degree in Electronic Engineering, 5 credits)


Prof. Valle

  • Technology and Circuit track
    • Register Transfer Level: basics
    • Flip-Flop and Latches circuit design
    • Power consumption in CMOS
    • Timing and timing analysis (basics)
    • Interconnect and interconnect modeling
    • Array subsystems  and FPGA
    • Metastability
    • Synchronizer and pipeline design
    • Design methodologies (basics) and design economics (e.g. NRE etc.)
  • VHDL design meth track
    • Overview of Hardware Description Languages
    • Basic Language Constructs
    • Concurrent Signal Assignment Statements
    • Sequential Statements
    • Synthesis of VHDL Code
    • Sequential Circuit Design
    • Finite State Machine: Principle and Practice
    • Register Transfer Design/Synthesis Methodology
    • Control and Data Paths: basics (i.e. FSMD)



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