(Master Degree in Electronic Engineering, 5 credits)

This course is aimed at providing the student with basic knowledge, methodology and skills required to approach the design of a Digital Integrated Circuit. Thanks to the wide industrial experience of the teachers, both actively involved in professional design activities, the course addresses the most up-to-date challenges in digital design and combines them with the solid technical background offered by the Integrated Electronic System course. In particular, the course covers a variety of topics which span from an overview of the digital design methodology flow to the advanced verification techniques.

This also includes an introduction to the System Verilog Language for both design and verification and a boot camp on the Universal Verification Methodology (UVM). Given the complexity of the topics to cover, the course will include examples of how to apply the discussed tecniques and methodologies to real design. This course has the ambition of introducing the knowledge of UVM in the student curricula. This is because such topic is gaining a rapidly growing importance in the industrial community and more importantly the success of each design project heavily relies on effective and exhaustive verification approach.